1. Field of Invention
The present invention relates to a planarization process. More particularly, the present invention relates to a planarization process that solves the problem of microscratches caused by chemical-mechanical polishing.
2. Description of Related Art
With the steady improvement in integrated circuit (IC) fabrication, the multi-conductive layer has become a standard structure in semiconductor technologies. The material and position of the dielectric layers are increasingly important. Because of the requirement for high resolution for photolithography, the planarization of dielectric layer has been emphasized. The traditional methods of planarization for semiconductor technologies are spin-on glass (SOG) and chemical-mechanical polishing (CMP). SOG is for local planarization, and CMP is for global planarization. Of the two processes, CMP is used more frequently.
FIGS. 1A-1C are schematic, cross-sectional views of a conventional planarization process for manufacturing a dielectric layer.
In FIG. 1A, semiconductor devices (not shown) are formed on a substrate 10. The substrate is, for example, a silicon substrate 10. Conducting wires 12 are formed on the substrate 10. An oxide layer 14 is formed on the substrate 10. The oxide layer 14 can be silicon-rich oxide (SRO) formed by plasma enhanced chemical vapor deposition (PECVD).
A SOG layer 16 is formed on the oxide layer 14. Because the SOG is a dielectric material dissolved in a chemical solvent, the SOG layer 16 can be formed by a spin-coating method in which planarization is performed by spreading chemical solvent with SOG material on the surface of the substrate 10. A thermal process, also known as a curing process, is performed to evaporate the chemical solvent and the SOG layer 16 is thus formed on the oxide layer 14. However, a small portion of the chemical solvent may be left in the SOG layer 16 after the curing process. The SOG layer 16 is exposed by a contact hole and then undergoes an O.sub.2 -plasma bombarding process and an amine-solvent embedding process. Electrophilic groups are therefore formed in SOG layer 16 and water molecules are subsequently absorbed. Next, a metallization process is performed at a very high temperature which allows the absorbed water molecules to evaporate and leave the SOG layer 16. It is also highly possible that the water molecules are trapped in metal to produce voids, which poison the metal. Therefore, an ion-implantation process, with ions such as arsenic ions, is performed during the curing process. The bonds between solvent molecules and the dielectric material can be broken by ions with sufficient dynamic energy. The ions take the place of the solvent molecules and the solvent molecules are thus removed from the dielectric material. This means that the top portion of the SOG layer 16 is transformed to an ion-doped SOG layer 18 and that the electrophilic ability is largely reduced in order to prevent out-gassing problem from occurring in the metallization process.
An oxide layer 20 is formed on the planarized SOG layer 16. The oxide layer 20 can be formed by plasma enhanced chemical vapor deposition (PECVD), for example. An inter-metal dielectric with a sandwich structure is formed by the three oxide layers 14, 16, 20.
Referring to FIG. 1B, the oxide layer 20 is polished by a chemical-mechanical polishing process to obtain a globally planarized dielectric layer. Because of the existence of microparticles, the chemical-mechanical polishing process will cause microscratch 22 on the surface of the oxide layer 20. The metal is deposited into the microscratch 22 and a metal bridge 24 is thus formed during the following metallization process. Existence of the metal bridge 24 over the microscratch 22 may lead to a connection between two independent conducting wires.
Referring to FIG. 1C, conventional method for avoiding metal bridges is to form a cap oxide layer 26 on the polished oxide layer 20. But voids can also be produced during the process of cap oxide layer 26 filling the microscratch.